1. Technical Field
The invention relates generally to semiconductor devices, and more specifically, to chip-on-chip packaging in semiconductor devices.
2. Background Art
Considerable advancement has occurred in the last fifty years in electronic development and packaging. Integrated circuit density has and continues to increase at a significant rate. However, by the 1980s, the increase in density in integrated circuitry was not being matched with a corresponding increase in density of the interconnecting circuitry external of circuitry formed within a chip. Many new packaging technologies have emerged. One specific technology is referred to as "chip-on-chip module" technology. This invention concerns the specific art area of chip-on-chip modules.
In many cases, chip-on-chip modules can be fabricated faster and more cheaply than by designing new substrate integrated circuitry. Chip-on-chip module technology is advantageous because of the density increase. With increased density comes equivalent improvements in signal propagation speed and overall device weight unmatched by other means. Current chip-on-chip module construction typically consists of a printed circuit board substrate to which a series of integrated circuit components are directly adhered.
There are further a number of distinct art areas associated with how a substrate adhered circuit of a chip-on-chip module is electrically externally connected to circuitry on the substrate. These art areas include wire bonding, tape automated bonding (TAB), flip-TAB and flip-chip. Some examples are found in the following U.S. Patents: U.S. Pat. No. 5,323,060, "Multichip Module Having a Stacked Chip Arrangement", issued June 1994 to Fogal el al.; U.S. Pat. No. 5,600,541, "Vertical IC Chip Stack With Discrete Chip Carriers Formed From Dielectric Tape", issued February 1997 to Bone et al.; U.S. Pat. No. 5,495,394, "Three Dimensional Die Packaging in Multi-chip Modules", issued February 1996 to Komeld et al.; and U.S. Pat. No. 5,399,898, "Multi-Chip Semiconductor Arrangements Using Flip Chip Dies", issued March 1995 to Rostoker.
Unfortunately these technologies are expensive and in most cases do not allow rework (i.e., removal and replacement) of the package constituents; thereby decreasing the yield and increasing the cost. Chip-scale personalization is also severely limited. Currently chips can be personalized at the wafer-level or the package-level. The inability to personalize a chip post-wafer fabrication but before packaging does not allow significant product application flexibility and manufacturing cost advantages.